1. Field of the Invention
The present invention is directed to a programmable controller, and more particularly to such a programmable controller capable of executing complicate instructions in addition to fundamental sequential control instructions for operation of associated I/O and peripheral devices.
2. Description of the Prior Art
In recent years there have been a growing demand for programmable controllers which can be utilized in many application fields where a great amount of data are to be processed. To this end the programmable controllers are required to execute a complicate program in order to handle the increased amount of data for achieving a sophisticated control over associated I/O and peripheral devices. In other words, as the sophisticated control are required, the program itself becomes more complicated so as to include, in addition to "basic instructions" for sequential control of the I/O devices, many "applied instructions" for processing of the great amount of the data such as by arithmetic and logic operations. However, as the number of such applied instructions becomes greater, the programmable controller has to wait the completion of the instruction executions before accessing the I/O devices, resulting in a critical delay in response. That is, the programmable controller in which the instruction execution is carried out in a cyclic scan mode, there has been a considerably increased scan time for the execution of the instructions, which fails to give a real-time response of practically acceptable level. In addition, it is also required in keeping the real-time response to use the applied instructions which themselves can be rapidly executed in the programmable controller. Further, there is a trend that the program becomes more and more complicated with attendant increase in the program length or size in order to attain the sophisticated control. To compress the program size as well as to make such complicated program readily understandable by the user, the applied instruction itself becomes more and more complex to contain more than several words. In view of program development efficiency, there is expected a growing tendency to use a high-level language, for example, a SFC (sequence functional chart) language with a readily understandable program rather than conventional assembly languages with mnemonic operation codes because the use of the assembly language may involve awkward debugging operations. Consequently, the programmable controllers are increasingly being called upon to keep real-time response capability for different high-level languages that the user prefers. In other words, it is essential for the programmable controllers performing sophisticated controls to perform execution of the complex applied instructions as fast as possible and to have design flexibility to different high-level languages.
The prior art programmable controllers can be classified into the following two types depending upon the modes of handling the basic and applied instructions in obtaining fast execution of the instruction. Prior to proceeding the description, it is confirmed that the "applied instruction" is defined in this text to require a multi-bit operation for data processing in order to store an input data temporarily into a memory, to transfer the data into another memory, to perform add/subtract/multiply/divide operations, or to perform data conversion, while the "basic instruction" is defined to refer to a single-bit operation including a logical operation in order to input and output a control signal from and to the I/O devices for monitoring and actuating the devices, and to obtain logical AND/OR output.
1) Separate processing mode
The basic instructions which account for a large proportion of a user program is processed by a specifically designed hardware logic, while the applied instructions are software-processed at a general CPU; and
2) Improved separate processing mode
Large proportion of the applied instructions are processed also by a specifically designed hardware logic which is controlled by an additional processor (coprocessor) relying upon a large number of microcodes or microprograms.
From a viewpoint of enhancing processing efficiency, the programmable controller operating in the above mode 2) is found to be advantageous. The programmable controller having such concept has been proposed in U.S. Pat. No. 4,694,419. However, in the prior art programmable controller relying upon the microcodes for processing the applied instructions, the number of microcodes will increase greatly as the applied instruction becomes more and more complex, necessitating a huge memory space for the microcodes as well as a correspondingly complicated control logic which should be implemented to include FIFO memory and an instruction queue into an architecture under the limitations of the instructions. As illustrated in FIG. 1 the prior art programmable controller can be shown in a schematic diagram to comprise a source instruction memory 10 storing a source program including complex applied instructions in addition to basic instructions, a microcode memory 11 storing microprogram associated with the applied instructions, a main processor 12, a system memory 13 storing an operating system for the main processor 12 and providing a work area utilized by the main processor 12, a coprocessor 14, and a data memory 15 utilized by the coprocessor 14. An I/O and peripheral interface 16 is provided to actuate associated I/O devices and peripheral devices under the control of the main processor 12. The main processor 12 is responsible for operation of the coprocessor 14. The coprocessor 14 is provided to read instructions directly from the source instruction memory 10 and then fetch suitable information from the microcode memory 11 in order to execute the instructions, the result of which is passed to the main processor 12 for control of the I/O and peripheral devices. These units are interconnected by means of address and data buses B1 to B4.
In the meanwhile, the instructions are preferably pipelined to obtain a high-speed processing at the coprocessor 14. Such pipeline processing is most efficient when the instruction fetch, decode and execution stages are arranged to occur continuously. However, with the prior programmable controller using the instructions relying upon the microcodes, the complex instructions may requires two or more words per one instruction. This means that when a multi-word instruction follows a single word instruction, several stages or cycles are required to fetch the instruction straddling over the several words before execution of that instruction, causing a delay between the execution cycle of the preceding single word instruction and the execution cycle of the following multi-word instruction. Further, in the above prior art configuration, microcode fetch and the computation of the corresponding microcode memory address require at least one cycle in which no instruction fetch is permitted. Therefore, prefetch of a next instruction is only possible during the execution of the current instruction and not during the microcode fetch or address calculation of the microcode memory. These limitations pose considerable hindrance to the high-speed pipelined processing. Furthermore, the prefetch of the multi-word instruction requires a correspondingly large instruction queue memory. When a branch instruction is designated in the multi-word instruction, the instruction or instructions already entered in the instruction queue must be canceled to thereby give a loss cycle or cycles. Therefore, the prior art configuration requires a large instruction queue memory and suffers from the loss cycle or cycles in proportion to the size of the queue memory, which should be avoided from the standpoint of reducing the cost-consuming memory as well as of attaining high speed processing.
The like problems are encountered in a general 32-bit micro processor referred to as CISC [complex instruction set computer] which includes huge microcodes to meet with more and more complex instructions, in which considerable efforts are being made to compress the microcode fetch cycle and to reduce the loss cycles at branch instruction in the pipelined processing.
The instruction processing to be performed in the prior art programmable controller of FIG. 1 will be now explained with regard to "MV" (move) instruction which is one of the applied instructions. The MV instruction is in the form of a 5-words (1 word=16 bits) instruction within the source code which, as shown in FIG. 2, comprises an operation code (op code) MV, lower operand and upper operands related to a source [src] address including operand modification, lower and upper operands related to a destination [dest] address including operand modification. For execution of the instruction, the programmable controller of FIG. 1 is configured to have separate datapaths respectively to the system memory 13 and the data memory 15, and is enabled to prefetch at least one word instruction for pipelining. FIG. 3 illustrates a timing sequence for execution of the instruction consisting of fetch & decode stage [in which instruction fetch, microcode fetch, and decode are performed] and execution & operation stage [in which memory access to data memory 15 as well as computation between registers are performed]. At the first stage, the operation code [op code] for MV instruction is prefetched and decoded in parallel with the execution of the preceding instruction and therefore this fetch & decode stage is not counted in the number of a total bus cycles for completion of the MV instruction. This is true in the execution of the normal instructions except for special instructions such as branch and interrupt instructions which requires to cancel the prefetch. In the next 2 bus cycles, microcode memory address in microcode memory 11 is calculated based upon the prefetched op code and the corresponding microcode is fetched. After the microcode fetch, the sequence proceeds to perform updating of the address of the source instruction memory 10, control of the following fetch, updating of the instruction queue in the coprocessor 14, control of the following microcode fetch, and into execution & operation stage in association with the op code. It is noted at this time that although the microcode fetch is illustrated to be performed in 2 bus cycles, the like microcode fetch may occur simultaneously in the fetch & decode stage from source instruction memory 10 as well as in the execution & operation stage of the instruction. Subsequently, lower and upper operands related to the source information are fetched sequentially in order to determine source [src] address. It is not until the second fetch stage is completed to fetch the upper operand that the coprocessor 14 does not operate to read the corresponding source address data from data memory 15 and transfer that data internally into the coprocessor 14. Thus, the memory access to read and transfer the source address data is performed at the next cycle in parallel with the fetch of the lower operand related to the destination information. Then, the upper operand related to the destination information is fetched and decoded to determine destination [dest] address within a next one cycle. Finally, the coprocessor 14 operates to write back the data retrieved from the source [src] address to the destination [dest] address of the data memory 15 to finish the instruction [MV] in one cycle in parallel with the prefetch of a next instruction op code. Consequently, in order to complete the MV instruction the prior programmable controller requires 7 consecutive cycles beginning from the microcode fetch cycles to the write back data cycle. It is possible with this prior art programmable controller to reduce the bus cycles from 7 to 6 by suitable configuring the op code such that the lower operand fetch can be made in parallel with the microcode fetch & microcode memory address calculation. In any event, however, the prior art programmable controller requires as many as 6 or 7 bus cycles, since the microcode fetch is inevitable for the execution of the instruction. As described in the above, it has been a general practice in the prior art programmable controller to rely upon microcodes for processing a number of complex applied instructions at the coprocessor with the use of the microcode memory in order to meet with changes in specific tasks set by the user, while keeping the internal logic of the coprocessor at a simple configuration and at the same time utilizing a hardware logic for execution of the simple basic instructions which does not need to rely upon the microcodes.
Apart from the high-speed execution of the user program, there should be considered a scan time in order to reduce a total processing time. As shown in FIG. 4, the scan time T in the above prior programmable controller comprises, in addition to a time T2 for execution of the instruction in the source instruction memory, a time T1 for conducting an I/O service, i.e, for access to the I/O devices to be controlled, a time T3 for communication with particular peripheral devices such as computers, program writer, printers or the like. That is, the above three tasks are serially performed within one scan time T. As apparent from FIG. 4, a total scan time T is therefore the sum of the T1, T2, and T3, requiring rather elongated scan time for completing one instruction, which contradicts to the real time response required in the programmable controller.